The present invention relates generally to non-volatile memory cells and more specifically to a technique for reducing the erratic operation of such cells caused by the build up of holes at specific locations during the operation of the cells.
FIG. 1 illustrates a typical prior art non-volatile memory cell generally designated by reference numeral 10. Memory cell 10 includes a silicon substrate 12 containing a doubly diffused source 14 and a drain 16. Substrate 12 supports a tunnel oxide layer 18, a floating gate 20, an ONO dielectric layer 22, and a gate 24. Memory cell 10 also includes an electrical lead 26 connected to drain 16, an electrical lead 28 connected to gate 24, and an electrical lead 30 connected to source 14. These leads are used for programming and erasing the memory cell. The particular prior art memory cell 10 shown in FIG. 1 is turned on by applying 6V to drain 16, 12V to gate 24, and grounding source 14 through their respective leads. The memory cell is erased by applying 12V to source 14 and grounding both drain 16 and gate 24, again through their respective leads.
During the electrical erasing process, prior art memory cells are known to have the problem of band to band tunneling which is the build up of holes at a particular location within the cell, specifically underneath tunnel oxide layer 18 at the junction between the source 14 and the tunnel oxide layer. FIG. 2 is an energy diagram of the prior art memory cell shown in FIG. 1. This energy diagram illustrates the flow of electrons from the floating gate into the source as the memory cell is being electrically erased. At the same time holes are counter injected from the source into the tunnel oxide and build up within the tunnel oxide along the junction with the source. This build up of holes erratically changes the threshold voltage of each cell within an array of memory cells which causes a wide threshold voltage distribution among the memory cells making up the array. The threshold voltage of a cell is the minimum voltage required for the cell to be conductive from source 14 to drain 16. This wide threshold voltage distribution among the memory cells making up the array makes it difficult to determine whether the cells have been erased properly and this problem is referred to as an erratic erase problem.
Several arrangements have been proposed which attempt to reduce the erratic erase problem described above including using graded source/drain junctions as illustrated in FIG. 1. This arrangement uses a doubly diffused source, or a deep source, to allow a larger voltage of 12V to be used during the electrical erasing of the cell. Using the graded source/drain and the 12V during the erasing reduces but does not solve the erratic erase problem. Because of the light and deep source, this approach also limits the ability to physically scale down this arrangement beyond a certain point. Some of the other arrangements which attempt to reduce the erratic erase problem include graded gate oxides, lightly doped drains in combination with negative gate erase, double Fowler-Nordhiem injection, and an algorithmic approach to self-convergence. Although these approaches are currently being used, they still are susceptible to the erratic erase problem. They also may create other problems such as reduced durability or increased complexity and expense of manufacture. The present invention provides a more reliable approach to solving this erratic erase problem.